In the fabrication of integrated circuits, lithography is used to generate pattern structures on the semiconductor and various materials for the construction of the desired circuit structures. A continuing demand in view of the ever increasing desire in the semiconductor industry for higher circuit density in microelectronic devices has prompted lithographic engineers to develop improved lithographic processes. As the circuit density of semiconductor devices increases, higher resolution of circuit patterns in resist films is increasingly demanded. One way of improving the resolution in resist is to migrate to shorter wavelength from 365 nm to 248 nm, then to 193 and 157 nm, and further to extremely short optical wavelengths like EUV (extreme ultraviolet), or to adopt non optical system such as E-beam. The EUV lithography with exposure wavelengths below 20 nm would allow the industry to print features beyond the diffraction limit of the current 193 nm lithography without resorting to the adoption of tricks using double or triple patterning. Nevertheless, the adoption of EUV technology has been delayed for several times due to its limitations in power source for meeting throughput requirement in manufacturing. In addition, the equipment and mask for EUV lithography are very expensive. Therefore, it is highly desirable to provide a new method to produce fine features without requiring the use of new and more expensive tooling. One technique emerged, which only requires ArF (193 nm) deep UV (DUV) immersion lithography in combination with spacer deposition, is called sidewall image transfer (SIT). This spacer based SIT technique can print very fine features by doubling, quadrupling or sextupling the pattern density with multiple deposition and etching schemes.
The fin field effect transistor (FinFET) has advantages over bulk metal oxide semiconductor FET (MOSFET) in the aspects of: reduced leakage, excellent sub-threshold slop, and better voltage gain without degradation of noise or linearity. Therefore, FinFET structure is desired device architecture for high end devices such as microprocessors. In fabricating FinFET, small fin width keeps the short channel effect under control, and small fin pitch enables comparable or even higher area efficiency in terms of the current per device width ratio. Small fin pitch is extremely difficult to fabricate especially when the pitch sizes reach sub 30 nm or sub 20 nm range in the future device generations. Double SIT and triple SIT processes provide ways to fabricate fin structures with pitch sizes in this range. Although Furukawa et al., in U.S. Pat. No. 6,875,703, teach a method of making a quadruple density SIT structure, and Chen, in U.S. Pat. No. 8,524,605, teaches a method of forming patterned features having pitch reduced to one sixth of the original value defined by the minimum resolution of a lithographic tool, they are not practical for fabricating fin structures with sub 30 nm fin pitch. Therefore, there is a need to have a new SIT process to be able to fabricate sub 30 or sub 20 nm fin pitches in FinFET fabrication.